With the continuous development of semiconductor manufacturing technology, the pattern critical dimension of the integrated circuit chips is becoming smaller and smaller, therefore, the requirement for the detecting method is becoming higher and higher. For example, after forming a metal layer at the CMOS BEOL process, a leakage current test would be needed to adjacent patterns or lines in the metal layer, in order to avoid the occurrence of the short circuit between the adjacent patterns or the lines.
Referring now to FIG. 1, which is a schematic view illustrating a test layout for leakage current in a metal layer and a cross section of the test layout in the prior art. As shown in the FIG. 1, because the leakage current in the metal layer is very slim in nature, the current of a single detecting element (the minimum square in the test layout) is so small that beyond the minimum precision of a test device. Therefore, a plurality of the single detecting elements are paralleled to increase the total current, then the leakage current of the single detecting element is received by a calculation.
Shown in the FIG. 1, a detecting element of the test layout is fragmentary enlarged. It is found that the detecting element employed by the prior art is usually formed by two-group separate comb structures staggered, of which one group is connected to the high potential, and another group is connected to the low potential. In addition, the cross-sectional schematic view of the test layout shown on the right of the FIG. 1 has shown that two-group patterns in the first metal layer are arrayed in turn. Therefore, once the short circuit occurs between any two adjacent metal lines, a big leakage current would the detected.
In the actual process, the test layouts, which are utilized to monitor the occurrence of the short circuit during the process, are usually arranged in the empty space between chips on the substrate. With the continuous decreasing of the chip size, more detecting elements of the test layout shown in the FIG. 1 are required to measure effectively the leakage current. It is well known that the more the detecting elements are, the more the empty space is needed. However, on the contrary, the development of the IC technology requires the decreasing of the empty space on the substrate to make more room for more chips, so that increasing the number of chips output.
Therefore, how to get the results with high accuracy on the condition of the decreasing area of the test layout for detecting leakage current becomes an urgent problem at present in the field of semiconductor IC manufacturing technology.